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The FE-I4 pixel readout integrated circuit

Fast facts

  • Internal authorship

    Prof. Dr. Michael Karagounis

  • Further publishers

    M. Garcia-Sciveres, D. Arutinov, M. Barbero, R. Beccherle, S. Dube, D. Elledge, J. Fleury, D. Fougeron, F. Gensolen, D. Gnani, V. Gromov, T. Hemperek, R. Kluit, A. Kruth, A. Mekkaoui, M. Menouni, J.-D. Schipper

  • Publishment

    • 2011

  • Journal

    Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment (1, Supplement)

  • Organizational unit

    Electrical engineering

  • Subjects

    • General electrical engineering

  • Publication format

    Journal article (Article)

Content

A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.

Keywords

130nm

ATLAS upgrades

High luminosity

Pixel detector

Notes and references

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