Zitat
P. Pangaud et al., “Test results and irradiation performances of 3-D circuits developed in the framework of ATLAS hybrid pixel upgrade,” in 2010 IEEE Nuclear Science Symposium Conference Record, Piscataway, NJ: IEEE, 2010, pp. 1551–1555. doi: 10.1109/nssmic.2010.5874036
Abstract
Vertex detectors for High Energy Physics experiments require pixel detectors featuring high spatial resolution, very good signal to noise ratio and radiation hardness. A way to face new challenges of ATLAS/SLHC future hybrid pixel vertex detectors is to use the emerging 3-D Integrated Technologies. However, commercial offers of such technologies are only very few and the 3-D designer’s choice is then hardly constrained. Moreover, as radiation hardness and specially SEU tolerance of configuration registers is a crucial issue for SLHC vertex detectors and, as commercial data on this point are always missing, a reliable qualification program is to be developed for any candidate technology. We will present the design and test (including radiation tests with 70 kV, 60W X-Ray source and 24 GeV protons) of Chartered, 130nm Low Power 2-D chips realized for this qualification.
Referenzen und Relationen
DOI 10.1109/nssmic.2010.5874036
Schlagwörter
Detectors
Latches
Layout
MOS devices
Pixel
Radiation effects
Transistors