Abstract
The phase II upgrade of the HL-LHC experiments within the LHC intends to deepen the studies of the Higgs boson and to allow the discovery of further particles by adding an integrated luminosity of about 4000 fb-1 over 10 years of operation. This upgrade would overwhelm the installed pixel detector readout chips with higher hit rates and radiation levels than ever before. To match these extreme requirements the RD53 collaboration, a joint effort between ATLAS and CMS, developed RD53A, a new generation pixel detector readout chip prototype manufactured in a 65 nm CMOS technology. It is half the size of the final pixel chips and designed to meet requirements in the face of 3 GHz/cm2 hit rate after irradiation to 500 Mrad. The detector is able to use 50×50μm2 or 25×100μm2 pixels with high readout speed of up to 4 links per chip with 1.28 Gbit/s each. Shunt–LDO regulators integrated on the bottom of the chip provide the required voltages to the two power domains, analog and digital. These regulators enable serial powering of the pixel modules, which is the only feasible, radiation hard scheme to ensure acceptable power cable losses and to stay within the material budget for the future pixel detectors. An overview of the status and challenges of serial powering and the Shunt–LDO regulator development will be given.
Schlagwörter
Front end electronics for detector readout
RD53A
Serial powering