Content
A new pixel Front-End Integrated Circuit is being developed in a 130nm technology for use in the foreseen b-layer upgrade of the ATLAS Pixel Detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel Front-End. The new digital architecture logic is not based on a transfer of all pixel hits to the End-of-Column, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the Double-Column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.
Keywords
Buffer storage
Detectors
Digital integrated circuits
Integrated circuit technology
Iron
Large Hadron Collider
Logic
Nuclear and plasma sciences
Physics
Prototypes