Development of a counting strip detector readout chip for precision compton polarimetry

A strip detector readout chip used in an individual photon counting detection system for precision Compton polarimetry has been chosen as a platform for the implementation, comparison and the in-silicon test of several alternative architectural analog and digital circuit concepts. For this application first an analytic result for the noise optimization has been derived based on the EKV model which gives the optimum width of the input transistor of the charge sensitive amplifier as a function of the inversion factor. Apart from the input transistor, the noise contribution from the biasing for a folded and a telescopic cascode preamplifier topology has also been analyzed. The limitations of conventional shaping circuits using MOS transistors operating in linear region as feedback elements are emphasized and alternative shaping topologies based on linearized transconductance amplifier are introduced. A potential hazard of synchronous counters reacting on very short clock pulses is described which becomes much less severe when the implementation is changed to asynchronous ripple counters. All digital circuitry has been implemented in Differential Current Logic to reduce crosstalk between the digital and the analog circuitry. The trade-offs which are related to the presented architectural options are extracted from measurements and simulations.

Circuit noise

Circuit testing

Circuit topology

Counting circuits

Crosstalk

Detectors

Polarimetry

Pulse amplifiers

Strips

System testing