Content
Recently, applications in high energy physics are considering the use of RISC-V microprocessors in harsh radiation environments. In this paper, we present the STRV-R1, a first RISC-V processor design adapted to ensure sufficient tolerance to radiation-induced soft errors in a near-beamline LHC environment and to enable the development of microprocessor-based systems in such environments. We compare the resource overhead imposed by the TMR based protection scheme with an unprotected design. The processor was exposed to 1 degree TID to verify adequate hardness against long-term cumulative ionizing damage. Pulsed laser and heavy ion irradiations were performed to characterize the response of the design to radiation-induced soft errors. Over the different irradiation configurations, the cross sections for SEFIs were improved by up to 8000× compared to the SEU cross section by introducing TMR-based soft error protection. This reduction in cross section resulted in a 5.12× increase in the cell count of the processor design compared to the unprotected design and a 4.96× increase in the required power budget. During irradiation, it was observed that in systems with complex combinatorial logic, such as a RISC-V microprocessor core, the SEEs are predominantly caused by SETs.
Keywords
Fault tolerance
RISC-V
Radiation testing
Redundancy
Single event effects
Triple modular redundancy