Zitat
A. Qamesh et al., “SEU characterization of the MOPS-Hub FPGA for the new ATLAS ITk pixel detector,” Journal of Instrumentation, vol. 20, no. 3, 2025, doi: 10.1088/1748-0221/20/03/c03051
Abstract
The upcoming ATLAS Phase II upgrade mandates replacing the tracking system with the all-silicon Inner Tracker (ITK), featuring a pixel detector as its core element. The monitoring data of the new system will be aggregated from an on-detector ASIC, Monitoring Of Pixel System (MOPS), and channeled to the Detector Control System (DCS) via a newly developed FPGA-based interface known as MOPS-Hub. This work evaluates the MOPS-Hub FPGA’s susceptibility to Single-Event Upsets (SEUs) through proton irradiation tests. An SEU rate of 7 upsets/day is estimated in the ITK radiation environment. To enhance fault tolerance and system resilience, mitigation techniques — including Triple Modular Redundancy (TMR) and using Soft Error Mitigation (SEM) IP — are implemented and assessed. © 2025 IOP Publishing Ltd and Sissa Medialab. All rights, including for text and data mining, AI training, and similar technologies, are reserved.
Referenzen und Relationen
DOI 10.1088/1748-0221/20/03/c03051